Exemplary embodiments of the present invention relate to a memory device and a method for fabricating the same, and more particularly, to a vertical channel type nonvolatile memory device and a method for fabricating the same.
A nonvolatile memory device is a memory device in which stored data is maintained even though a power is not supplied. As the degree of integration increases, a fabrication of a memory device having a two-dimensional structure, i.e., a memory device having memory cells fabricated in a single layer over a silicon substrate, may reach limits. Thus, a nonvolatile memory device having a three-dimensional structure, i.e., a memory device having memory cells that are vertically stacked over a silicon substrate, may be used.
Referring to the paper released on 2007, “H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, entitled ‘Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,’ 2007 Symposium on VLSI Technology Digest of Technical Papers, Page(s): 14-15,” by forming the string of a NAND flash memory device vertically from a substrate, the degree of integration can be significantly increased when compared to the conventional two-dimensional memory device.
In a NAND flash memory device having the three-dimensional structure as described above, data may be stored in a charge storage layer, e.g., a charge trap layer such as a nitride layer. Referring to the paper released on 2004, “White, M. H., Adams, D. A., Murray, 3. R., Wrazien, S., Yijie Zhao, Yu Wang, Khan, B., Miller, W., and Mehrotra, R., entitled ‘Characterization of Scaled SONOS EEPROM Memory Devices for Space and Military Systems’, Non-Volatile Memory Technology Symposium, 15-17 Nov. 2004 Page(s): 51-59”, data can be stored using a nitride layer instead of a conventional floating gate electrode.
Hereafter, the construction of a conventional nonvolatile memory device having a three-dimensional structure and the problems occurred therein will be described in detail with reference to a drawing.
FIG. 1 is a cross-sectional view illustrating the construction of a conventional nonvolatile memory device having a three-dimensional structure. FIG. 1 specifically illustrates the cross-section of a vertical channel type nonvolatile memory device.
Referring to FIG. 1, in a conventional vertical channel type nonvolatile memory device, a lower selection transistor LST, a plurality of memory cells MC, and an upper selection transistor UST may be sequentially stacked along channels CH which are vertically arranged on the surface of a substrate 10.
A method for fabricating the vertical channel type nonvolatile memory device constructed as mentioned above will be briefly described below.
An interlayer dielectric layer 11 and a conductive layer 12 for a gate electrode may be stacked on the substrate 10 which include underlying structures required for the operation of a cell array. Subsequently, a trench may be formed by etching the interlayer dielectric layer 11 and the conductive layer 12 for a gate electrode.
After forming a gate dielectric layer 13 on the inner surfaces of the trench, a channel CH may be formed by filling the trench with a material for a channel layer. In this way, the lower selection transistor LST may be formed.
A plurality of interlayer dielectric layers 11 and a plurality of conductive layers 12 may be alternately stacked on the resultant structure including the lower selection transistor LST. By etching the plurality of interlayer dielectric layers 11 and the plurality of conductive layers 12, a trench which exposes the channel CH of the lower selection transistor LST may be formed.
After sequentially forming a charge blocking layer, a charge trap layer and a tunnel isolation layer 14 on the inner surfaces of the trench, a channel CH may be formed by filling the trench with a layer for a channel. In this way, the plurality of memory cells MC may be formed along the channel CH which is vertically arranged on the substrate 10.
An interlayer dielectric layer 11 and a conductive layer 12 for a gate electrode may be stacked on the resultant structure including the plurality of memory cells MC. Subsequently, a trench may be formed by etching the interlayer dielectric layer 11 and the conductive layer 12 for a gate electrode to expose the channel CH of the memory cells MC.
After forming a gate dielectric layer 15 on the inner surfaces of the trench, a channel CH may be formed by filling the trench with a layer for a channel. In this way, the upper selection transistor UST may be formed.
However, in the conventional art as described above, the charge trap layer may be formed on the inner surfaces of the trench. Therefore, a resultant structure in which the charge trap layers of the plurality of memory cells MC are stacked along the channel CH may be connected with one another, and accordingly, charges may migrate among adjoining memory cells MC. The migration of the charges may cause a shift of the threshold voltages (Vt) of the memory cells MC, and thus the cycling characteristics and data retention characteristics of the memory device may deteriorate. Thus, the reliability of the memory device may deteriorate.
Such a problem is described in detail in the paper released on 2004, “Lusky, E., Shacham-Diamand, Y., Mitenberg, G., Shappir, A., Bloom, I., Eitan, B., entitled ‘Investigation of Channel Hot Electron Injection by Localized Charge-trapping Nonvolatile Memory Devices’, Electron Devices, IEEE Transactions on Volume 51, Issue 3, March 2004 Page(s): 444-451.”
Meanwhile, in the case of a charge storage layer such as a polysilicon layer, for storing charges in a conductive band, the charges stored in the charge storage layer can freely migrate. In other words, the charges can more freely migrate in the polysilicon layer than in the charge trap layer which traps charges in a deep level trap site.
Accordingly, it is difficult to apply the charge storage layer such as the polysilicon layer, in which charges can freely migrate, to the vertical channel type nonvolatile memory device constructed as described above, because not only the reliability of the memory device may not be secured due to the migration of charges between adjoining memory cells, but also the memory cells may not operate properly.